Possible solution to *E,EXPLPA … expecting a left parenthesis …error message

I was getting the following error message when I was initially creating a Verilog testbench

irun: 11.10-s062: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
file: ./phy_tst.v
   logic [3:0]  TXN;
         |
ncvlog: *E,EXPLPA (./phy_tst.v,44|9): expecting a left parenthesis (‘(‘) [12.1.2][7.1(IEEE)].
   logic [3:0]  TXN;
                   |
ncvlog: *E,EXPLPA (./phy_tst.v,44|19): expecting a left parenthesis (‘(‘) [12.1.2][7.1(IEEE)].
    module worklib.phy_tst:v
        errors: 2, warnings: 0
ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances.
irun: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 2)

The solution is to add the +sv switch to your simulation command line

irun +sv phy_tst.v

I hope that helps someone out there 😉

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